1. Technical Field
The embodiments described herein relate to an electrostatic discharge device, and more particularly, to an electrostatic discharge device which has a decreased layout area.
2. Related Art
Conventional semiconductor device often include an electrostatic discharge device, which is connected between an input/out (I/O) pad and an internal circuit. When a semiconductor device comes into contact with a charged human body or machine, static electricity can flow to the internal circuit through the I/O pad. In such instances, the electrostatic discharge device protects the internal circuit from the static electricity.
As semiconductor technologies trend toward higher speed operation and increased integration, the thickness of the insulation layer of transistor gates included in the internal circuits is decreasing. As a result, the voltage level at which the insulation layer is destroyed, i.e., as a result of static electricity, also decreases in proportion to the decrease in the thickness of the insulation layer. Therefore, it is becoming more difficult to design an electrostatic discharge device with sufficient margin to protect the internal circuits from, e.g., static electricity.
FIG. 1 is a diagram illustrating a conventional electrostatic discharge device. The conventional electrostatic discharge device includes a capacitor C1 and a resistor R2 for detecting static electricity.
When static electricity is introduced through an input/output pad (I/O), protection elements 102 and 104 discharge the static electricity introduced through the input/output pad (I/O) to the line connected to a power supply voltage (Vcc) terminal and to the line connected to a ground voltage (Vss) terminal. At this time, a transistor 103 discharges the static electricity flowing to an input buffer via the voltage applied to a resistor R1, and the gate oxide layer of the transistor included in the input buffer is protected from the static electricity.
If a voltage difference occurs between the line connected to the power supply voltage (Vcc) terminal and the line connected to the ground voltage (Vss) terminal due to the static electricity, then a voltage resulting from the static electricity is applied to a capacitor C1 and a resistor R2, and a power clamp element 105 discharges the static electricity via the voltage applied to the gate thereof.
The diode 104 of FIG. 1 has a configuration as shown in FIG. 2. The diode 104 is formed over a P-well. A P+ junction area and an N+ junction area are separated from each other by an STI layer, the N+ junction area comes into contact with the input/output pad I/O, and the P+ junction area comes into contact with the line connected to the ground voltage (Vss) terminal.
The diode 102 of FIG. 1 has a configuration as shown in FIG. 3. The diode 102 is formed over an N-well. A P+ junction area and an N+ junction area are separated from each other by an STI layer, the P+ junction area comes into contact with the input/output pad I/O, and the N+ junction area comes into contact with the line connected to the power supply voltage (Vcc) terminal.
The electrostatic discharge device shown in FIG. 1 has an advantage in that it has a low triggering voltage. However, in the electrostatic discharge device shown in FIG. 1, the capacitor C1 and the resistor R2 provided to drive the power clamp element 105 are designed to have a large area in order to handle the threshold voltage of the power clamp element 105, and must be installed for each input/output pad I/O. This clearly has an adverse effect on the chip area.
The area demand and the fact that the capacitor C1 and the resistor R2 for driving the power clamp element 105 must be installed for each input/output pad I/O can impose a substantial burden in terms of chip size, the detrimental effect of which is heightened due to the increased integration and reduce chip size of today's semiconductor devices.